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2024-4-25
Ft Worth, TX
PGAs · Experienced with design and simulation tools (Xilinx Vivado, Microsemi Libero, Mentor QUESTASim) · Experience with Perl, Visual Basic, and C/C , · DO 178C/254 verification · High Speed and RF design · Cadence schematic capture, PCB layout Allegro · Atlassian Tools (Jira, Bitbucket, Confluence) · Strong Written and Oral Communication Skills · Aerospace Product Development Experience · Agile Development Experience · Technical requirement development, decomposition, verification experience · Veri
2024-4-19
Humble, TX
growth opportunities as the sky is the limit so aim for the stars Imagine next and join the Parsons QUESTAPPLY TODAY 30244137303
2024-4-22
Baltimore, MD
FPGA design implementation tools for IP integration PnR CDC such as Xilinx Vivado Intel Quartus and QUESTASim. Experience with industry standard ASIC front-end design tools for synthesis LEC CDC Experience with STA constraints generation and timing closure Experience with MATLAB Mentor Graphics design tools Synopsys or similar tool Familiarity with Xilinx and Intel FPGA technology This position is contingent upon transfer of DoD Secret Clearance and Special Program Access (SAP) prior to starting. Salary Range: $112600 - $169000 The above salary range represents a gen
2024-4-25
Baltimore, MD
FPGA design implementation tools for IP integration PnR CDC such as Xilinx Vivado Intel Quartus and QUESTASim. Working knowledge of full product life cycle (requirements design implementation and test) of FPGA Design and/or ASIC Design Knowledge of System Verilog Verilog and/or VHDL Preferred Qualifications: Advanced Degrees in Electrical Engineering Computer Engineering Computer Science or related technical fields Active DoD Top Secret Clearance or higher Experience with industry standard ASIC front-end design tools for synthesis LEC CDC Experience with STA
2024-4-25
Baltimore, MD
FPGA design implementation tools for IP integration PnR CDC such as Xilinx Vivado Intel Quartus and QUESTASim. Experience with industry standard ASIC front-end design tools for synthesis LEC CDC Experience with STA constraints generation and timing closure Experience with MATLAB Mentor Graphics design tools Synopsys or similar tool Familiarity with Xilinx and Intel FPGA technology This position is contingent upon transfer of DoD Secret Clearance and Special Program Access (SAP) prior to starting. Salary Range: $112600 - $169000 The above salary
2024-4-19
Baltimore, MD
FPGA design implementation tools for IP integration PnR CDC such as Xilinx Vivado Intel Quartus and QUESTASim. Working knowledge of full product life cycle (requirements design implementation and test) of FPGA Design and/or ASIC Design Knowledge of System Verilog Verilog and/or VHDL Preferred Qualifications: Advanced Degrees in Electrical Engineering Computer Engineering Computer Science or related technical fields Active DoD Top Secret Clearance or higher Experience with industry standard ASIC front-end design tools for synthesis LEC CDC Expe
2024-4-19
Wayne, NJ
ence VHDL proficiency for design entry Test bench and simulation expertise with Mentor Graphics QUESTASim Experience with standard vendor toolsets (Intel Quartus Xilinx Vivado) in Windows and/or Linux environments Lab verification and debugging Configuration management tools (Git) Architectural experience Motivated individual with strong problem-solving abilities Ability to mentor and lead a team of engineers Preferred Education Experience & Skills Active Secret Security Clearance Eligible for Top Secret Security Clearance Digital Signal Processing
2024-4-25
Burlington, MA
stemVerilog/UVM, OVM, and/or VHDL Experience with FPGA/ASIC design and verification tools (Mentor QUESTA or Cadence) Proven track record of managing and executing to schedules, and driving tasks to closure. Candidates should also be comfortable multitasking because they may be asked to support multiple projects. Strong communication and documentation skills Experience developing and implementing test plans. Abilty to work effectively in a multi-site or borderless environment Preferred Education, Experience, & Skills The following skills/experience are preferred
2024-4-25
Burlington, MA
SystemVerilog/UVM OVM and/or VHDL Experience with FPGA/ASIC design and verification tools (Mentor QUESTA or Cadence) Proven track record of managing and executing to schedules and driving tasks to closure. Candidates should also be comfortable multitasking because they may be asked to support multiple projects. Strong communication and documentation skills Experience developing and implementing test plans. Abilty to work effectively in a multi-site or borderless environment Preferred Education Experience & Skills The following skills/experience are preferred bu
2024-4-25
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2024-4-25
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